SFERA Archivio dei prodotti della Ricerca dell'Università di Ferrara

BERTOZZI, Davide
 Distribuzione geografica
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Continente #
NA - Nord America 16.682
AS - Asia 8.557
EU - Europa 3.706
SA - Sud America 1.312
AF - Africa 172
OC - Oceania 20
Continente sconosciuto - Info sul continente non disponibili 5
Totale 30.454
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Nazione #
US - Stati Uniti d'America 16.414
SG - Singapore 3.309
CN - Cina 2.146
BR - Brasile 1.030
VN - Vietnam 944
UA - Ucraina 772
HK - Hong Kong 692
DE - Germania 646
IT - Italia 538
TR - Turchia 522
GB - Regno Unito 420
FI - Finlandia 298
FR - Francia 259
JP - Giappone 230
RU - Federazione Russa 213
SE - Svezia 187
IN - India 157
MX - Messico 134
PL - Polonia 127
AR - Argentina 101
CA - Canada 97
BD - Bangladesh 96
IQ - Iraq 83
ID - Indonesia 68
ZA - Sudafrica 65
AT - Austria 58
EC - Ecuador 50
PK - Pakistan 47
ES - Italia 46
CO - Colombia 39
NL - Olanda 38
SA - Arabia Saudita 33
MA - Marocco 31
PH - Filippine 31
UZ - Uzbekistan 26
BE - Belgio 22
MY - Malesia 21
TN - Tunisia 21
VE - Venezuela 21
CL - Cile 20
TW - Taiwan 19
PY - Paraguay 17
KE - Kenya 15
AE - Emirati Arabi Uniti 14
LT - Lituania 14
IL - Israele 13
JO - Giordania 13
OM - Oman 13
AU - Australia 12
EG - Egitto 12
RS - Serbia 11
UY - Uruguay 11
AZ - Azerbaigian 10
BO - Bolivia 10
NP - Nepal 10
PE - Perù 10
CZ - Repubblica Ceca 7
IR - Iran 7
NZ - Nuova Zelanda 7
DO - Repubblica Dominicana 6
DZ - Algeria 6
ET - Etiopia 6
KW - Kuwait 6
AL - Albania 5
CR - Costa Rica 5
HN - Honduras 5
IE - Irlanda 5
JM - Giamaica 5
KR - Corea 5
KZ - Kazakistan 5
RO - Romania 5
BY - Bielorussia 4
DK - Danimarca 4
GE - Georgia 4
HR - Croazia 4
KG - Kirghizistan 4
PA - Panama 4
AF - Afghanistan, Repubblica islamica di 3
BG - Bulgaria 3
CH - Svizzera 3
EE - Estonia 3
EU - Europa 3
GA - Gabon 3
GR - Grecia 3
NI - Nicaragua 3
PS - Palestinian Territory 3
QA - Qatar 3
TH - Thailandia 3
A2 - ???statistics.table.value.countryCode.A2??? 2
AM - Armenia 2
AO - Angola 2
BH - Bahrain 2
BN - Brunei Darussalam 2
GY - Guiana 2
KH - Cambogia 2
LB - Libano 2
LU - Lussemburgo 2
LV - Lettonia 2
LY - Libia 2
MU - Mauritius 2
Totale 30.422
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Città #
Singapore 2.165
Ashburn 2.024
Fairfield 1.964
Woodbridge 1.713
Houston 1.147
Jacksonville 867
Seattle 790
Beijing 746
Ann Arbor 730
Santa Clara 717
Hong Kong 686
Wilmington 675
San Jose 672
Cambridge 631
Chandler 631
Ho Chi Minh City 354
Izmir 320
Nanjing 268
Hanoi 239
Tokyo 227
Princeton 197
Los Angeles 189
Milan 177
Lauterbourg 167
Munich 163
Boardman 162
Addison 160
Ferrara 160
San Diego 153
Dallas 141
New York 129
Warsaw 121
Helsinki 110
Shanghai 92
São Paulo 92
Mexico City 86
Chicago 77
Shenyang 71
Nanchang 62
Council Bluffs 51
Tianjin 50
Orem 49
London 45
Vienna 45
Brooklyn 44
San Francisco 42
Hefei 41
Chennai 40
Falkenstein 40
Hebei 40
Da Nang 39
Jiaxing 39
Montreal 39
Haiphong 38
Moscow 38
The Dalles 38
Baghdad 37
Frankfurt am Main 36
Stockholm 35
Changsha 33
Johannesburg 33
Mountain View 32
Boston 30
Turku 30
Atlanta 29
Norwalk 29
Redwood City 27
Rio de Janeiro 27
Zhengzhou 26
Tashkent 25
Toronto 25
Amsterdam 24
Indiana 24
Jakarta 24
Brasília 23
Auburn Hills 21
Bologna 21
Brussels 21
Phoenix 21
Curitiba 20
Des Moines 20
Guangzhou 20
Jinan 20
Orange 20
Barnet 19
Belo Horizonte 19
Denver 19
Ningbo 19
Washington 19
Dhaka 17
Nuremberg 17
Quito 17
Ankara 16
Guayaquil 16
Lahore 16
New Delhi 16
Salvador 16
San Mateo 16
Biên Hòa 15
Columbus 15
Totale 21.798
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Nome #
SSDExplorer: a Virtual Platform for Performance/Reliability-oriented Fine-Grained Design Space Exploration of Solid State Drives 298
Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System 283
A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip 273
A network model for routing-fault-free wavelength selection in WRONoCs design 246
System interconnect extensions for fully transparent demand paging in low-cost MMU-less embedded systems 243
Logic programming approaches for routing fault-free and maximally parallel wavelength-routed optical networks-on-chip (Application paper) 242
Evolutionary vs. Revolutionary Interconnect Technologies for Future Low-Power Multi-Core Systems 232
Network-on-chip architectures and design methods 230
Partitioning Strategies of Wavelength-Routed Optical Networks-on-Chip for Laser Power Minimization 230
PROTON+: A placement and routing tool for 3d optical networks-on-chip with a single optical layer 228
Integrated Cross-Layer Solutions for Enabling Silicon Photonics into Future Chip Multiprocessors 227
A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories 223
Populating and exploring the design space of wavelength-routed optical network-on-chip topologies by leveraging the add-drop filtering primitive 223
Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers 218
Technology-Aware Communication Architecture Design for Parallel Hardware Platforms 217
Cooperative built-in self-testing and self-diagnosis of NOC bisynchronous channels 216
Analysis of reliability/performance trade-off in Solid State Drives 215
Engineering a Bandwidth-Scalable Optical Layer for a 3D Multi-core Processor with Awareness of Layout Constraints 213
Ultra-low latency NoC testing via pseudo-random test pattern compaction 211
A Built-In Self-Testing Framework for Asynchronous Bundled-Data NoC Switches Resilient to Delay Variations 210
Exploring Communication Protocols for Optical Networks-on-Chip based on Ring Topologies 209
Crossbar replication vs. sharing for virtual channel flow control in asynchronous NoCs: A comparative study 209
Energy-Efficient Network on Chip Design 208
Non-intrusive trace & debug NoC architecture with accurate timestamping for GALS SoCs 208
Increasing Impartiality and Robustness in High-Performance N-Way Asynchronous Arbiters 208
Abstract Modelling of Switching Elements for Optical Networks-on-Chip with Technology Platform Awareness 207
A vertically integrated and interoperable multi-vendor synthesis flow for predictable noc design in nanoscale technologies 207
Dynamically Reconfigurable NoC using a deadlock-free flexible routing algorithm with a low hardware implementation cost 207
Augmenting manycore programmable accelerators with photonic interconnect technology for the high-end embedded computing domain 206
Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration 205
Dyafnoc: Dynamically reconfigurable noc characterization using a simple adaptive deadlock-free routing algorithm with a low implementation cost 205
Contrasting wavelength-routed optical NoC topologies for power-efficient 3d-stacked multicore processors using physical-layer analysis 204
Cost-effective and flexible asynchronous interconnect technology for GALS networks-on-chip 202
A Fast and Accurate Technique for Mapping Parallel Applications on Stream-Oriented MPSoC Platforms with Communication Awareness 200
Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline 199
NoC-centric partitioning and reconfiguration technologies for the efficient sharing of multi-core programmable accelerators 198
Allocation and Scheduling for MPSoCs via decomposition and no-good generation 197
The design predictability concern in optical network-on-chip design 197
A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems 197
Cost-Effective Contention Avoidance in a CMP with Shared Memory Controllers 197
Bottom-Up Abstract Modelling of Optical Networks-on-Chip: From Physical to Architectural Layer 196
Power efficiency of wavelength-routed optical NoC topologies for global connectivity of 3D multi-core processors 195
Contrasting Power Efficiency of Contention Resolution vs. Avoidance Strategies in Optical Ring Interconnects for Photonically-Integrated Embedded Systems 195
Correlating Power Efficiency and Lifetime to Programming Strategies in RRAM-Based FPGAs 194
Resource Management Policy Handling Multiple Use-Cases in MPSoC Platforms Using Constraint Programming 192
State-of-the-Art SoC Communication Architectures 192
Process Variation and Layout Mismatch Tolerant Design of Source Synchronous Links for GALS Networks-on-Chip 191
A tool for synthesizing power-efficient and custom-tailored wavelength-routed optical rings 189
Allocation and Scheduling for MPSoCs via Decomposition and No-Good Generation 188
A Cooperative, accurate solving framework for optimal allocation, scheduling and frequency selection on energy-efficient MPSoCs 188
Exploiting Network-on-Chip Structural Redundancy for A Cooperative and Scalable Built-In Self-Test Architecture 187
OSR-Lite: Fast and deadlock-free NoC reconfiguration framework 187
An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart 187
Design technology for fault-free and maximally-parallel wavelength-routed optical networks-on-chip 186
Bringing Network-on-Chip Links to 45nm 185
Design Space Exploration of a Mesochronous Link for Cost-Effective and Flexible GALS NOCs 185
Xpipes: a Latency Insensitive Parameterized Network-on-Chip Architecture for Multi-Processor SoCs 185
A fast algorithm for runtime reconfiguration to maximize the lifetime of nanoscale NoCs 184
Moonrake Chip - GALS Demonstrator in 40 nm CMOS Technology 182
Contrasting Topologies for Regular Interconnection Networks under the Constraints of Nanoscale Silicon Technology 182
SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives 182
Variation tolerant NoC design by means of self-calibrating links 180
Power efficiency of switch architecture extensions for fault tolerant NoC design 180
A high-efficiency wind-flow energy harvester using micro turbine 180
Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology 179
A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devices 179
Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches 178
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints 178
Control- and Data-Path Decoupling in the Design of a NoC Switch: Area, Power and Performance Implications 177
System-Level Infrastructure for Boot-time Testing and Configuration of Networks-on-Chip with Programmable Routing Logic 177
Exploring the Performance-Energy Optimization Space of a Bridge Between 3D-Stacked Electronic and Optical Networks-on-Chip 177
Optimizing built-in pseudo-random self-testing for network-on-chip switches 176
Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework. 175
Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms 174
A Retrospective Look at Xpipes: The Exciting Ride from a Design Experience to a Design Platform for Nanoscale Networks-on-Chip 174
Energy-Reliability Trade-Off for NoCs 173
Transparent Lifetime Built-In Self-Testing of Networks-on-Chip Through the Selective Non-Concurrent Testing of their Communication Channels 173
Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip 172
Power-Optimal RTL Arithmetic-Unit Soft-Macro Selection Strategy for Leakage-Sensitive Technologies 170
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC 170
Exploiting structural redundancy of SIMD accelerators for their built-in self-testing/diagnosis and reconfiguration. 170
Flexible DOR Routing for Virtualization of Multicore Chips 169
Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip 169
Contrasting Multi-Synchronous MPSoC Design Styles for Fine-Grained Clock Domain Partitioning: the Full-HD Video Playback Case Study 169
Battery Lifetime Optimization for Energy-Aware Circuits 168
Performance analysis of arbitration policies for SoC communication architectures 168
Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints 168
Designing Network On-Chip Architectures in the Nanoscale Era 168
Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style 167
A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration 167
Design automation beyond its electronic roots: toward a synthesis mothodology for wavelength-routed optical networks-on-chip 167
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing 166
Accurate Assessment of Bundled-Data Asynchronous NoCs Enabled by a Predictable and Efficient Hierarchical Synthesis Flow 166
Non Volatile Memory Partitioning Scheme for Technology-based Performance-Reliability Trade-off 165
Efficient Implementation of Distributed Routing Algorithms for NoCs 164
Design Space Exploration of Wavelength-Routed Optical NoC Topologies for 3D-Stacked Multi- and Many-Core Processors. 161
Application-specific power-aware workload allocation for voltage scalable MPSoC platforms 160
Reducing the Abstraction and Optimality Gaps in the Allocation and Scheduling for Variable Voltage/Frequency MPSoC Platforms 160
Network Interface Sharing Techniques for Area Optimized NoC Architectures 160
Spice-Accurate SystemC Macromodels of Noisy On-Chip Communication Channels 160
Totale 19.354
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Categoria #
all - tutte 132.342
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 14.195
Totale 146.537
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021706 0 0 0 0 0 0 0 0 0 356 227 123
2021/20222.065 104 204 206 21 75 118 118 96 59 161 245 658
2022/20231.732 202 21 49 205 263 249 161 177 225 16 100 64
2023/2024776 90 116 49 26 59 77 40 60 5 22 17 215
2024/20253.707 104 104 345 91 479 497 78 166 477 457 575 334
2025/202610.611 1.079 591 941 1.346 1.812 623 1.287 603 1.205 1.124 0 0
Totale 30.774