SFERA Archivio dei prodotti della Ricerca dell'Università di Ferrara

BERTOZZI, Davide
 Distribuzione geografica
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Continente #
NA - Nord America 17.462
AS - Asia 8.719
EU - Europa 3.777
SA - Sud America 1.319
AF - Africa 171
OC - Oceania 20
Continente sconosciuto - Info sul continente non disponibili 5
Totale 31.473
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Nazione #
US - Stati Uniti d'America 17.138
SG - Singapore 3.360
CN - Cina 2.193
BR - Brasile 1.032
VN - Vietnam 944
UA - Ucraina 775
HK - Hong Kong 696
DE - Germania 646
IT - Italia 587
TR - Turchia 522
GB - Regno Unito 425
FI - Finlandia 298
FR - Francia 260
JP - Giappone 230
RU - Federazione Russa 213
SE - Svezia 187
IN - India 157
BD - Bangladesh 151
CA - Canada 136
MX - Messico 136
PL - Polonia 129
AR - Argentina 102
IQ - Iraq 83
ID - Indonesia 70
ZA - Sudafrica 65
AT - Austria 58
EC - Ecuador 49
ES - Italia 49
PK - Pakistan 47
CO - Colombia 40
NL - Olanda 39
SA - Arabia Saudita 33
MA - Marocco 31
PH - Filippine 31
UZ - Uzbekistan 26
BE - Belgio 23
VE - Venezuela 22
MY - Malesia 21
CL - Cile 20
TN - Tunisia 20
PY - Paraguay 19
TW - Taiwan 19
KE - Kenya 15
AE - Emirati Arabi Uniti 14
LT - Lituania 14
IL - Israele 13
JO - Giordania 13
OM - Oman 13
AU - Australia 12
EG - Egitto 12
JM - Giamaica 12
RS - Serbia 12
UY - Uruguay 12
AZ - Azerbaigian 10
BO - Bolivia 10
NP - Nepal 10
PE - Perù 10
CR - Costa Rica 9
CZ - Repubblica Ceca 8
IR - Iran 7
KW - Kuwait 7
NZ - Nuova Zelanda 7
DZ - Algeria 6
ET - Etiopia 6
HN - Honduras 6
AL - Albania 5
DO - Repubblica Dominicana 5
IE - Irlanda 5
KR - Corea 5
KZ - Kazakistan 5
RO - Romania 5
BY - Bielorussia 4
DK - Danimarca 4
GE - Georgia 4
GT - Guatemala 4
HR - Croazia 4
KG - Kirghizistan 4
MD - Moldavia 4
PA - Panama 4
TH - Thailandia 4
AF - Afghanistan, Repubblica islamica di 3
BG - Bulgaria 3
CH - Svizzera 3
EE - Estonia 3
EU - Europa 3
GA - Gabon 3
GR - Grecia 3
KH - Cambogia 3
NI - Nicaragua 3
PS - Palestinian Territory 3
QA - Qatar 3
A2 - ???statistics.table.value.countryCode.A2??? 2
AM - Armenia 2
AO - Angola 2
BH - Bahrain 2
BN - Brunei Darussalam 2
GY - Guiana 2
LB - Libano 2
LU - Lussemburgo 2
LV - Lettonia 2
Totale 31.437
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Città #
Singapore 2.173
Ashburn 2.092
Fairfield 1.964
Woodbridge 1.713
Houston 1.152
Jacksonville 867
San Jose 850
Seattle 791
Beijing 757
Santa Clara 753
Ann Arbor 730
Hong Kong 690
Wilmington 675
Cambridge 631
Chandler 631
Ho Chi Minh City 356
Izmir 320
Nanjing 268
Hanoi 239
Tokyo 226
Los Angeles 205
Princeton 197
Milan 182
Lauterbourg 167
Munich 163
New York 163
Boardman 162
Addison 160
Dallas 154
Ferrara 154
San Diego 154
Council Bluffs 131
Warsaw 121
Helsinki 110
Shanghai 92
São Paulo 92
Mexico City 87
Chicago 86
Shenyang 71
Nanchang 62
Orem 53
Tianjin 51
Brooklyn 50
London 47
Toronto 47
San Francisco 46
Vienna 45
Montreal 41
Chennai 40
Falkenstein 40
Hebei 40
Hefei 40
Da Nang 39
Jiaxing 39
Moscow 39
Haiphong 38
The Dalles 38
Baghdad 37
Atlanta 36
Frankfurt am Main 36
Changsha 35
Stockholm 35
Johannesburg 33
Mountain View 32
Boston 30
Turku 30
Norwalk 29
Redwood City 28
Rio de Janeiro 28
Zhengzhou 26
Bologna 25
Phoenix 25
Tashkent 25
Amsterdam 24
Indiana 24
Jakarta 24
Brasília 23
Brussels 22
Buffalo 22
Auburn Hills 21
Washington 21
Curitiba 20
Denver 20
Des Moines 20
Guangzhou 20
Jinan 20
Orange 20
Barnet 19
Belo Horizonte 19
Ningbo 19
Columbus 18
Dhaka 18
Manchester 17
Nuremberg 17
Quito 17
Rome 17
Ankara 16
Lahore 16
New Delhi 16
Salvador 16
Totale 22.340
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Nome #
SSDExplorer: a Virtual Platform for Performance/Reliability-oriented Fine-Grained Design Space Exploration of Solid State Drives 327
Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System 301
A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip 280
Logic programming approaches for routing fault-free and maximally parallel wavelength-routed optical networks-on-chip (Application paper) 253
A network model for routing-fault-free wavelength selection in WRONoCs design 252
System interconnect extensions for fully transparent demand paging in low-cost MMU-less embedded systems 245
Partitioning Strategies of Wavelength-Routed Optical Networks-on-Chip for Laser Power Minimization 239
Evolutionary vs. Revolutionary Interconnect Technologies for Future Low-Power Multi-Core Systems 238
PROTON+: A placement and routing tool for 3d optical networks-on-chip with a single optical layer 236
Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers 235
Network-on-chip architectures and design methods 234
Populating and exploring the design space of wavelength-routed optical network-on-chip topologies by leveraging the add-drop filtering primitive 232
Integrated Cross-Layer Solutions for Enabling Silicon Photonics into Future Chip Multiprocessors 231
A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories 226
Cooperative built-in self-testing and self-diagnosis of NOC bisynchronous channels 222
Engineering a Bandwidth-Scalable Optical Layer for a 3D Multi-core Processor with Awareness of Layout Constraints 219
Non-intrusive trace & debug NoC architecture with accurate timestamping for GALS SoCs 219
Technology-Aware Communication Architecture Design for Parallel Hardware Platforms 219
Crossbar replication vs. sharing for virtual channel flow control in asynchronous NoCs: A comparative study 218
Analysis of reliability/performance trade-off in Solid State Drives 216
A vertically integrated and interoperable multi-vendor synthesis flow for predictable noc design in nanoscale technologies 215
Exploring Communication Protocols for Optical Networks-on-Chip based on Ring Topologies 214
Increasing Impartiality and Robustness in High-Performance N-Way Asynchronous Arbiters 214
Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration 213
Dyafnoc: Dynamically reconfigurable noc characterization using a simple adaptive deadlock-free routing algorithm with a low implementation cost 213
Ultra-low latency NoC testing via pseudo-random test pattern compaction 212
A Built-In Self-Testing Framework for Asynchronous Bundled-Data NoC Switches Resilient to Delay Variations 212
Dynamically Reconfigurable NoC using a deadlock-free flexible routing algorithm with a low hardware implementation cost 211
Energy-Efficient Network on Chip Design 210
Abstract Modelling of Switching Elements for Optical Networks-on-Chip with Technology Platform Awareness 210
Augmenting manycore programmable accelerators with photonic interconnect technology for the high-end embedded computing domain 210
Contrasting wavelength-routed optical NoC topologies for power-efficient 3d-stacked multicore processors using physical-layer analysis 209
Bottom-Up Abstract Modelling of Optical Networks-on-Chip: From Physical to Architectural Layer 208
The design predictability concern in optical network-on-chip design 208
A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems 204
A Fast and Accurate Technique for Mapping Parallel Applications on Stream-Oriented MPSoC Platforms with Communication Awareness 204
Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline 204
Contrasting Power Efficiency of Contention Resolution vs. Avoidance Strategies in Optical Ring Interconnects for Photonically-Integrated Embedded Systems 204
NoC-centric partitioning and reconfiguration technologies for the efficient sharing of multi-core programmable accelerators 204
Cost-effective and flexible asynchronous interconnect technology for GALS networks-on-chip 203
Correlating Power Efficiency and Lifetime to Programming Strategies in RRAM-Based FPGAs 203
Allocation and Scheduling for MPSoCs via decomposition and no-good generation 202
State-of-the-Art SoC Communication Architectures 199
Cost-Effective Contention Avoidance in a CMP with Shared Memory Controllers 198
Exploiting Network-on-Chip Structural Redundancy for A Cooperative and Scalable Built-In Self-Test Architecture 195
Power efficiency of wavelength-routed optical NoC topologies for global connectivity of 3D multi-core processors 195
A tool for synthesizing power-efficient and custom-tailored wavelength-routed optical rings 195
Resource Management Policy Handling Multiple Use-Cases in MPSoC Platforms Using Constraint Programming 194
Process Variation and Layout Mismatch Tolerant Design of Source Synchronous Links for GALS Networks-on-Chip 194
Allocation and Scheduling for MPSoCs via Decomposition and No-Good Generation 193
A Cooperative, accurate solving framework for optimal allocation, scheduling and frequency selection on energy-efficient MPSoCs 193
Bringing Network-on-Chip Links to 45nm 192
Design technology for fault-free and maximally-parallel wavelength-routed optical networks-on-chip 192
OSR-Lite: Fast and deadlock-free NoC reconfiguration framework 191
An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart 191
Xpipes: a Latency Insensitive Parameterized Network-on-Chip Architecture for Multi-Processor SoCs 189
Contrasting Topologies for Regular Interconnection Networks under the Constraints of Nanoscale Silicon Technology 188
A fast algorithm for runtime reconfiguration to maximize the lifetime of nanoscale NoCs 188
SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives 186
A high-efficiency wind-flow energy harvester using micro turbine 186
Moonrake Chip - GALS Demonstrator in 40 nm CMOS Technology 185
Design Space Exploration of a Mesochronous Link for Cost-Effective and Flexible GALS NOCs 185
Power efficiency of switch architecture extensions for fault tolerant NoC design 185
Exploring the Performance-Energy Optimization Space of a Bridge Between 3D-Stacked Electronic and Optical Networks-on-Chip 185
Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches 184
Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology 184
System-Level Infrastructure for Boot-time Testing and Configuration of Networks-on-Chip with Programmable Routing Logic 184
A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devices 184
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints 183
Control- and Data-Path Decoupling in the Design of a NoC Switch: Area, Power and Performance Implications 182
Optimizing built-in pseudo-random self-testing for network-on-chip switches 182
Variation tolerant NoC design by means of self-calibrating links 181
A Retrospective Look at Xpipes: The Exciting Ride from a Design Experience to a Design Platform for Nanoscale Networks-on-Chip 180
Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework. 179
Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style 178
Energy-Reliability Trade-Off for NoCs 178
Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip 178
Transparent Lifetime Built-In Self-Testing of Networks-on-Chip Through the Selective Non-Concurrent Testing of their Communication Channels 178
A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration 177
Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms 176
Exploiting structural redundancy of SIMD accelerators for their built-in self-testing/diagnosis and reconfiguration. 176
Performance analysis of arbitration policies for SoC communication architectures 175
Accurate Assessment of Bundled-Data Asynchronous NoCs Enabled by a Predictable and Efficient Hierarchical Synthesis Flow 175
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC 174
Contrasting Multi-Synchronous MPSoC Design Styles for Fine-Grained Clock Domain Partitioning: the Full-HD Video Playback Case Study 174
Power-Optimal RTL Arithmetic-Unit Soft-Macro Selection Strategy for Leakage-Sensitive Technologies 172
Battery Lifetime Optimization for Energy-Aware Circuits 172
Flexible DOR Routing for Virtualization of Multicore Chips 172
Non Volatile Memory Partitioning Scheme for Technology-based Performance-Reliability Trade-off 172
Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints 171
Designing Network On-Chip Architectures in the Nanoscale Era 171
Design automation beyond its electronic roots: toward a synthesis mothodology for wavelength-routed optical networks-on-chip 171
Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip 170
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing 169
Efficient Implementation of Distributed Routing Algorithms for NoCs 168
Power aware network interface management for streaming multimedia 167
Network-on-chip architectures and design methods 167
Network Interface Architecture and Design Issues 163
Design Space Exploration of Wavelength-Routed Optical NoC Topologies for 3D-Stacked Multi- and Many-Core Processors. 163
Concurrent network-on-chip lifetime testing through selective disconnection of its communication channels 163
Totale 19.921
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Categoria #
all - tutte 143.181
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 15.340
Totale 158.521
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2021/20222.065 104 204 206 21 75 118 118 96 59 161 245 658
2022/20231.732 202 21 49 205 263 249 161 177 225 16 100 64
2023/2024776 90 116 49 26 59 77 40 60 5 22 17 215
2024/20253.689 104 104 345 90 479 497 76 163 475 450 573 333
2025/202611.358 1.073 588 937 1.342 1.810 622 1.285 598 1.196 1.299 390 218
2026/2027289 289 0 0 0 0 0 0 0 0 0 0 0
Totale 31.792