Networks-on-chip (NoCs) are today at the core of multi- and many-core systems, acting as the system-level integration framework. In order to support scaling to future device generations, NoCs will struggle to deliver the required communication performance within tight power budgets. In this respect, evolutionary as well as revolutionary interconnect technologies are currently being considered. On one hand, clockless handshaking materializes GALS systems that completely remove the system clock while reducing idle power to only the leakage power. On the other hand, the technology platform could be changed, by replacing electrical wires with optical links and networks. This paper provides a comprehensive power analysis of the two technologies under test on a path-by-path basis, by comparing them with each other and with a baseline synchronous NoC. The outcome of this paper can support the selection of interconnect solutions for future manycore systems where power is the primary concern, as well as the runtime selection policy of routing paths in the context of hybrid interconnect fabrics.

Evolutionary vs. Revolutionary Interconnect Technologies for Future Low-Power Multi-Core Systems

Miorandi, G;Balboni, M;Ramini, L;Bertozzi, D
2016

Abstract

Networks-on-chip (NoCs) are today at the core of multi- and many-core systems, acting as the system-level integration framework. In order to support scaling to future device generations, NoCs will struggle to deliver the required communication performance within tight power budgets. In this respect, evolutionary as well as revolutionary interconnect technologies are currently being considered. On one hand, clockless handshaking materializes GALS systems that completely remove the system clock while reducing idle power to only the leakage power. On the other hand, the technology platform could be changed, by replacing electrical wires with optical links and networks. This paper provides a comprehensive power analysis of the two technologies under test on a path-by-path basis, by comparing them with each other and with a baseline synchronous NoC. The outcome of this paper can support the selection of interconnect solutions for future manycore systems where power is the primary concern, as well as the runtime selection policy of routing paths in the context of hybrid interconnect fabrics.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11392/2365530
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