We deliver a design flow for the synthesis and convergence of application-specific networks-on-chip. The flow comes with novel features that can better address nanoscale design challenges: front-end driven floorplanning, dynamic IR-drop minimization, fast and accurate system-level power grid modeling, predictable link design. Above all, such features are addressed by different prototype engines, even from different vendors, that can be smoothly integrated into the flow by means of a common specification format called Communication Exchange Format (CEF), that enables unprecedented tool interactions. This flow is validated by means of an extensive demonstration framework.

A vertically integrated and interoperable multi-vendor synthesis flow for predictable noc design in nanoscale technologies

GHIRIBALDI, Alberto
Primo
;
TATENGUEM FANKEM, Herve'
Secondo
;
BERTOZZI, Davide
Ultimo
2014

Abstract

We deliver a design flow for the synthesis and convergence of application-specific networks-on-chip. The flow comes with novel features that can better address nanoscale design challenges: front-end driven floorplanning, dynamic IR-drop minimization, fast and accurate system-level power grid modeling, predictable link design. Above all, such features are addressed by different prototype engines, even from different vendors, that can be smoothly integrated into the flow by means of a common specification format called Communication Exchange Format (CEF), that enables unprecedented tool interactions. This flow is validated by means of an extensive demonstration framework.
2014
9781479928163
Common specification, Exchange format, Floor-planning, Nano-scale design, Nanoscale technologies, Networks on chips, Power grid models, Prototype engine
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11392/2334907
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