Today, multi- and many-core architectures are gaining momentum as a potential source of hardware acceleration, bringing to new challenges for system designers related to both system virtualization and runtime testing. Our research activity tackles these challenges exploiting and optimizing the capabilities of reconfiguring the routing function at runtime.

NoC-centric partitioning and reconfiguration technologies for the efficient sharing of multi-core programmable accelerators

BERTOZZI, Davide;BALBONI, Marco
2015

Abstract

Today, multi- and many-core architectures are gaining momentum as a potential source of hardware acceleration, bringing to new challenges for system designers related to both system virtualization and runtime testing. Our research activity tackles these challenges exploiting and optimizing the capabilities of reconfiguring the routing function at runtime.
978-1-4673-7812-3
network-on-chip, runtime reconfiguration, routing function
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11392/2348484
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