Arbiters are the most critical element to manage a shared resource. Many arbiters in the literature are asynchronous, in order to improve concurrency and make the performance independent from the working frequency of the requesting clients. However, in asynchronous designs, architectural imbalances or variability can affect impartiality, such as latency equalization and arbitration fairness. Such a problem has largely not been taken into account in previous designs and experimental results. This work aims to perform an accurate rebalancing for N-way arbiters, using a new architecture, based on a tree structure. The proposed architecture drastically mitigates various forms of impartiality, as well as enhances overall robustness. The design is also scalable and highly performance-oriented. A detailed comparison of several post-layout N-way arbiter models is included. Results show significant benefits over most critical design costs.

Increasing Impartiality and Robustness in High-Performance N-Way Asynchronous Arbiters

MIORANDI, Gabriele
Primo
;
BERTOZZI, Davide
Secondo
;
2015

Abstract

Arbiters are the most critical element to manage a shared resource. Many arbiters in the literature are asynchronous, in order to improve concurrency and make the performance independent from the working frequency of the requesting clients. However, in asynchronous designs, architectural imbalances or variability can affect impartiality, such as latency equalization and arbitration fairness. Such a problem has largely not been taken into account in previous designs and experimental results. This work aims to perform an accurate rebalancing for N-way arbiters, using a new architecture, based on a tree structure. The proposed architecture drastically mitigates various forms of impartiality, as well as enhances overall robustness. The design is also scalable and highly performance-oriented. A detailed comparison of several post-layout N-way arbiter models is included. Results show significant benefits over most critical design costs.
2015
9781479987153
Computer architecture, Microprocessors, Logic gates, Robustness, Synchronization, System recovery,Tree Arbiters, Asynchronous, Arbiters
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11392/2333965
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