SFERA Archivio dei prodotti della Ricerca dell'Università di Ferrara

FAVALLI, Michele
 Distribuzione geografica
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Continente #
NA - Nord America 2.793
EU - Europa 562
AS - Asia 367
Continente sconosciuto - Info sul continente non disponibili 2
OC - Oceania 1
SA - Sud America 1
Totale 3.726
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Nazione #
US - Stati Uniti d'America 2.793
CN - Cina 266
UA - Ucraina 201
TR - Turchia 100
IT - Italia 99
DE - Germania 87
GB - Regno Unito 77
FI - Finlandia 49
SE - Svezia 25
FR - Francia 11
PL - Polonia 6
BE - Belgio 5
EU - Europa 2
RU - Federazione Russa 2
AU - Australia 1
BR - Brasile 1
IN - India 1
Totale 3.726
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Città #
Woodbridge 462
Fairfield 420
Houston 263
Jacksonville 216
Ashburn 200
Seattle 172
Wilmington 157
Chandler 154
Cambridge 149
Ann Arbor 131
Izmir 84
Nanjing 76
Beijing 66
Milan 50
Princeton 45
Addison 43
Boardman 36
San Diego 32
Ferrara 20
Shenyang 19
Shanghai 16
Nanchang 14
Hebei 13
Jiaxing 11
Norwalk 10
Helsinki 8
London 7
Tianjin 7
Bologna 6
Changsha 6
Jinan 6
Mountain View 6
Ningbo 6
Warsaw 6
Brussels 5
Indiana 5
Redwood City 5
Zhengzhou 5
Auburn Hills 4
Hangzhou 4
San Mateo 4
Kunming 3
New Bedfont 3
New York 3
Pensacola 3
Tappahannock 3
Verona 3
Changchun 2
Dresden 2
Falls Church 2
Haikou 2
Lanzhou 2
Los Angeles 2
Munich 2
Paris 2
Pavullo Nel Frignano 2
Prescot 2
Taizhou 2
Bagé 1
Boscoreale 1
Chicago 1
Dearborn 1
Des Moines 1
Harbin 1
Hefei 1
Jinhua 1
Noci 1
Orange 1
Padova 1
Portici 1
Pune 1
San Francisco 1
San Jose 1
Shaoxing 1
Sunnyvale 1
Wandsworth 1
Yellow Springs 1
Totale 3.008
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Nome #
A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits 160
Boolean and Pseudo-Boolean Test Generation for Feedback Bridging Faults 130
Bridging fault modeling and simulation for deep submicron CMOS ICs 110
Diversity analysis in the presence of delay faults affecting duplex systems 107
Testing Resistive Opens and Bridging Faults Through Pulse Propagation 106
A fuzzy model for path delay fault detection 105
Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-Checking Circuits 105
Annotated bit flip fault model 101
A Built-In Self-Testing Framework for Asynchronous Bundled-Data NoC Switches Resilient to Delay Variations 101
Power efficiency of switch architecture extensions for fault tolerant NoC design 100
How many test vectors we need to detect a bridging fault? 99
null 99
Exploiting Network-on-Chip Structural Redundancy for A Cooperative and Scalable Built-In Self-Test Architecture 99
High quality test vectors for bridging faults in the presence of IC's parameters variations 99
Pulse propagation for the detection of small delay defects 96
"Victim gate" crosstalk fault model 94
null 94
Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults 93
Self-checking scheme for the on-line testing of power supply noise 92
null 92
TMR voting in the presence of crosstalk faults at the voter inputs 91
Optimization of error detecting codes for the detection of crosstalk originated errors 90
Concurrent detection of power supply noise 89
Problems due to open faults in the interconnections of self-checking data-paths 87
On-Chip Clock Faults' Detector 87
System-Level Infrastructure for Boot-time Testing and Configuration of Networks-on-Chip with Programmable Routing Logic 86
Self-checking detection and diagnosis of transient, delay, and crosstalk faults affecting bus lines 85
Modeling and Simulation of Broken Connections in CMOS ICs 85
null 84
Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing 80
Regression models for behavioral power estimation 79
A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devices 78
Enabling testability of fault-tolerant circuits by means of I-DDQ-checkable voters 76
Symbolic handling of bridging fault effects 73
Correlation between IDDQ Testing Quality and Sensor Accuracy 62
Concurrent checking of clock signal correctness 62
Delay fault detection problems in circuits featuring a low combinational depth 61
Single Output Distribute Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures 60
Bridging Faults in Pipelined Circuits Journal of Electronic Testing, Theory and Applications 59
Test pattern generation for iddq: increasing test quality 58
null 48
A Complete Self-Testing and Self-Configuring NoC Infrastructure for Cost-Effective MPSoCs 21
A scalable bidimensional randomization scheme for tlc 3d nand flash memories 21
An evolutionary approach to the design of on chip pseudorandom test generators 14
Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits 13
Efficient testing of multi-output combinational cells in nano-complementary metal oxide semiconductor integrated circuits 12
The challenge of classification confidence estimation in dynamically-adaptive neural networks 11
Online testing approach for very deep-submicron ICs 9
Efficient Resource-Aware Neural Architecture Search with a Neuro-Symbolic Approach 5
Exploring Software Models for the Resilience Analysis of Deep Learning Accelerators: the NVDLA Case Study 4
Totale 3.772
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Categoria #
all - tutte 13.689
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 13.689
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/2019390 0 0 0 0 0 0 0 0 0 0 136 254
2019/2020970 165 38 30 141 68 107 88 101 76 72 67 17
2020/2021553 45 51 58 62 18 81 10 72 11 77 45 23
2021/2022448 12 39 40 20 14 24 33 22 8 37 47 152
2022/2023429 50 0 4 47 72 64 41 45 64 1 24 17
2023/2024126 26 22 8 6 16 11 14 12 5 3 3 0
Totale 3.772