SFERA Archivio dei prodotti della Ricerca dell'Università di Ferrara

FAVALLI, Michele
 Distribuzione geografica
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Continente #
NA - Nord America 2.927
EU - Europa 572
AS - Asia 499
Continente sconosciuto - Info sul continente non disponibili 2
OC - Oceania 1
SA - Sud America 1
Totale 4.002
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Nazione #
US - Stati Uniti d'America 2.927
CN - Cina 280
UA - Ucraina 201
SG - Singapore 113
IT - Italia 103
TR - Turchia 100
DE - Germania 89
GB - Regno Unito 77
FI - Finlandia 49
SE - Svezia 25
FR - Francia 11
PL - Polonia 6
BE - Belgio 5
ID - Indonesia 3
AT - Austria 2
EU - Europa 2
JP - Giappone 2
RU - Federazione Russa 2
AU - Australia 1
BR - Brasile 1
IN - India 1
LT - Lituania 1
LU - Lussemburgo 1
Totale 4.002
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Città #
Woodbridge 462
Fairfield 420
Houston 263
Jacksonville 216
Ashburn 200
Seattle 172
Wilmington 157
Chandler 154
Cambridge 149
Ann Arbor 131
Santa Clara 103
Izmir 84
Singapore 82
Nanjing 76
Beijing 66
Milan 50
Princeton 45
Addison 43
Boardman 37
San Diego 32
Ferrara 21
Shanghai 21
Shenyang 19
Nanchang 14
Hebei 13
Jiaxing 11
Norwalk 10
Helsinki 8
London 7
Tianjin 7
Bologna 6
Changsha 6
Jinan 6
Mountain View 6
Ningbo 6
Warsaw 6
Brussels 5
Indiana 5
Redwood City 5
Zhengzhou 5
Auburn Hills 4
Hangzhou 4
Los Angeles 4
San Mateo 4
Jakarta 3
Kunming 3
New Bedfont 3
New York 3
Pensacola 3
Tappahannock 3
Verona 3
Changchun 2
Dresden 2
Falls Church 2
Haikou 2
Lanzhou 2
Munich 2
Paris 2
Pavullo Nel Frignano 2
Prescot 2
Taizhou 2
Vienna 2
Bagé 1
Boscoreale 1
Chicago 1
Dearborn 1
Des Moines 1
Forest City 1
Harbin 1
Hefei 1
Jinhua 1
Luxembourg 1
Noci 1
Orange 1
Padova 1
Portici 1
Prineville 1
Pune 1
San Francisco 1
San Jose 1
Shaoxing 1
Sunnyvale 1
Turin 1
Wandsworth 1
Yellow Springs 1
Totale 3.211
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Nome #
A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits 167
Boolean and Pseudo-Boolean Test Generation for Feedback Bridging Faults 137
Bridging fault modeling and simulation for deep submicron CMOS ICs 117
Diversity analysis in the presence of delay faults affecting duplex systems 115
Annotated bit flip fault model 111
A fuzzy model for path delay fault detection 111
Testing Resistive Opens and Bridging Faults Through Pulse Propagation 111
A Built-In Self-Testing Framework for Asynchronous Bundled-Data NoC Switches Resilient to Delay Variations 109
Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-Checking Circuits 109
Exploiting Network-on-Chip Structural Redundancy for A Cooperative and Scalable Built-In Self-Test Architecture 108
Power efficiency of switch architecture extensions for fault tolerant NoC design 108
How many test vectors we need to detect a bridging fault? 104
High quality test vectors for bridging faults in the presence of IC's parameters variations 104
Pulse propagation for the detection of small delay defects 100
"Victim gate" crosstalk fault model 100
null 99
Concurrent detection of power supply noise 97
Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults 97
Self-checking scheme for the on-line testing of power supply noise 96
Optimization of error detecting codes for the detection of crosstalk originated errors 96
TMR voting in the presence of crosstalk faults at the voter inputs 95
null 94
System-Level Infrastructure for Boot-time Testing and Configuration of Networks-on-Chip with Programmable Routing Logic 94
null 92
Problems due to open faults in the interconnections of self-checking data-paths 91
On-Chip Clock Faults' Detector 91
Self-checking detection and diagnosis of transient, delay, and crosstalk faults affecting bus lines 89
Modeling and Simulation of Broken Connections in CMOS ICs 89
Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing 86
null 84
Regression models for behavioral power estimation 83
A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devices 83
Enabling testability of fault-tolerant circuits by means of I-DDQ-checkable voters 81
Symbolic handling of bridging fault effects 76
Correlation between IDDQ Testing Quality and Sensor Accuracy 70
Concurrent checking of clock signal correctness 69
Bridging Faults in Pipelined Circuits Journal of Electronic Testing, Theory and Applications 66
Delay fault detection problems in circuits featuring a low combinational depth 66
Single Output Distribute Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures 64
Test pattern generation for iddq: increasing test quality 62
null 48
A scalable bidimensional randomization scheme for tlc 3d nand flash memories 30
A Complete Self-Testing and Self-Configuring NoC Infrastructure for Cost-Effective MPSoCs 29
An evolutionary approach to the design of on chip pseudorandom test generators 21
Efficient Resource-Aware Neural Architecture Search with a Neuro-Symbolic Approach 21
The challenge of classification confidence estimation in dynamically-adaptive neural networks 20
Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits 19
Efficient testing of multi-output combinational cells in nano-complementary metal oxide semiconductor integrated circuits 16
Online testing approach for very deep-submicron ICs 15
Exploring Software Models for the Resilience Analysis of Deep Learning Accelerators: the NVDLA Case Study 10
Totale 4.050
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Categoria #
all - tutte 18.563
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 18.563
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/2020528 0 0 0 0 0 107 88 101 76 72 67 17
2020/2021553 45 51 58 62 18 81 10 72 11 77 45 23
2021/2022448 12 39 40 20 14 24 33 22 8 37 47 152
2022/2023429 50 0 4 47 72 64 41 45 64 1 24 17
2023/2024184 26 22 8 6 16 11 14 12 5 3 6 55
2024/2025220 11 21 88 5 95 0 0 0 0 0 0 0
Totale 4.050