statistiche ricercatore

Nome	#
Technology-Aware Communication Architecture Design for Parallel Hardware Platforms	121
Cooperative built-in self-testing and self-diagnosis of NOC bisynchronous channels	119
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints	105
Bringing Network-on-Chip Links to 45nm	102
Contrasting Topologies for Regular Interconnection Networks under the Constraints of Nanoscale Silicon Technology	100
null	99
Exploiting Network-on-Chip Structural Redundancy for A Cooperative and Scalable Built-In Self-Test Architecture	99
Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip	96
Design Space Exploration of a Mesochronous Link for Cost-Effective and Flexible GALS NOCs	94
null	89
System-Level Infrastructure for Boot-time Testing and Configuration of Networks-on-Chip with Programmable Routing Logic	86
Contrasting Multi-Synchronous MPSoC Design Styles for Fine-Grained Clock Domain Partitioning: the Full-HD Video Playback Case Study	68
A library of Dual-Clock FIFOs for Cost-Effective and Flexible MPSoCs Design	55
Mesochronous NoC Technology for Power-Efficient GALS MPSoC	51
null	42
A Complete Self-Testing and Self-Configuring NoC Infrastructure for Cost-Effective MPSoCs	21
Topology Exploration	7
The Synchronization Challenge	6
Totale	1.360

	Totale	Lug	Ago	Sett	Ott	Nov	Dic	Gen	Feb	Mar	Apr	Mag	Giu
2018/2019	147	0	0	0	0	0	0	0	0	0	0	52	95
2019/2020	371	60	14	12	51	25	38	28	37	24	44	33	5
2020/2021	197	17	23	5	36	8	21	4	28	1	25	18	11
2021/2022	181	16	23	16	0	6	11	10	10	4	12	23	50
2022/2023	130	15	1	1	9	23	17	14	12	21	1	10	6
2023/2024	39	7	8	4	3	7	8	0	0	2	0	0	0
Totale													1.360

SFERA Archivio dei prodotti della Ricerca dell'Università di Ferrara