The topology is a key factor for the performance and cost of any network-on-chip. Quality metrics and even feasibility of topologies are extremely sensitive to the performance of on-chip interconnects and to similar sutble design issues, with deep implications on the network architecture as well. This chapter moves from the awareness that many regular topologies feature better abstract properties than a 2-D mesh, however their silicon implementation is very challenging. The objective of this chapter is to quantify to which extent their inherently better abstract properties are impacted by the degradation effects of the physical implementation on nanoscale silicon technologies.
Topology Exploration
LUDOVICI, Daniele;BERTOZZI, Davide
2010
Abstract
The topology is a key factor for the performance and cost of any network-on-chip. Quality metrics and even feasibility of topologies are extremely sensitive to the performance of on-chip interconnects and to similar sutble design issues, with deep implications on the network architecture as well. This chapter moves from the awareness that many regular topologies feature better abstract properties than a 2-D mesh, however their silicon implementation is very challenging. The objective of this chapter is to quantify to which extent their inherently better abstract properties are impacted by the degradation effects of the physical implementation on nanoscale silicon technologies.I documenti in SFERA sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
