MEDARDONI, Simone
 Distribuzione geografica
Continente #
NA - Nord America 1.118
EU - Europa 352
AS - Asia 203
AF - Africa 3
Totale 1.676
Nazione #
US - Stati Uniti d'America 1.118
CN - Cina 137
PL - Polonia 136
UA - Ucraina 77
TR - Turchia 45
IT - Italia 41
DE - Germania 33
GB - Regno Unito 28
FI - Finlandia 19
SG - Singapore 18
SE - Svezia 12
MA - Marocco 3
BG - Bulgaria 2
ES - Italia 2
VN - Vietnam 2
DK - Danimarca 1
FR - Francia 1
ID - Indonesia 1
Totale 1.676
Città #
Fairfield 194
Woodbridge 138
Warsaw 136
Ashburn 127
Jacksonville 89
Houston 81
Seattle 71
Ann Arbor 66
Chandler 61
Cambridge 54
Wilmington 48
Beijing 31
Izmir 31
Nanjing 24
Shanghai 22
Milan 21
Princeton 17
Addison 16
Boardman 14
Singapore 12
San Diego 11
Wuhan 11
Washington 9
Jiaxing 8
Shenyang 7
Ferrara 6
Nanchang 6
Tianjin 5
Cagliari 4
Hebei 4
Helsinki 4
Mountain View 4
Zhengzhou 4
Auburn Hills 3
Casablanca 3
Changsha 3
San Mateo 3
Castellón 2
Dong Ket 2
Norwalk 2
Philadelphia 2
Redmond 2
Rome 2
Xiamen 2
Copenhagen 1
Des Moines 1
Falls Church 1
Guangzhou 1
Hangzhou 1
Indiana 1
Jakarta 1
Jinan 1
Ningbo 1
Prescot 1
Redwood City 1
Sofia 1
Taiyuan 1
Tappahannock 1
Totale 1.376
Nome #
Driving the Network-on-Chip Revolution to Remove the Interconnect Bottleneck in Nanoscale Multi-Processor Systems-on-Chip 211
Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms 110
Flexible DOR Routing for Virtualization of Multicore Chips 108
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints 107
Efficient Implementation of Distributed Routing Algorithms for NoCs 105
Variation tolerant NoC design by means of self-calibrating links 105
Network Interface Sharing Techniques for Area Optimized NoC Architectures 103
Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework. 102
Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip 101
Power-Optimal RTL Arithmetic-Unit Soft-Macro Selection Strategy for Leakage-Sensitive Technologies 100
Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints 100
null 98
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing 95
Yield-oriented Evaluation Methodology of Network-on-Chip Routing Implementations 92
Performance, Area and Power Breakdown Analysis for NoC Switches in 65nm Technology 75
Tight Integration of GALS Interfaces into the NoC Architecture 58
Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems 15
Totale 1.685
Categoria #
all - tutte 5.601
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 5.601


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/2020436 62 21 14 66 30 47 34 45 34 35 39 9
2020/2021241 27 25 14 26 12 31 10 29 4 30 20 13
2021/2022181 10 24 28 0 2 2 12 4 5 11 23 60
2022/2023154 18 0 0 19 33 24 17 11 22 0 7 3
2023/2024150 7 18 11 0 15 33 0 34 0 1 5 26
2024/20256 6 0 0 0 0 0 0 0 0 0 0 0
Totale 1.685