Leveraging a development effort of the synthesis backend for Networks-on-Chip (NoCs), this work contributes an analysis of the performance, area and power/energy breakdown of NoC switches in 65nm technology. In particular, an architecture-level technique (control- and data-path decoupling) is deployed to derive switch implementation variants optimized for different design objectives, and is then validated against placement-aware logic synthesis.
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Titolo: | Performance, Area and Power Breakdown Analysis for NoC Switches in 65nm Technology | |
Autori: | ||
Data di pubblicazione: | 2007 | |
Abstract: | Leveraging a development effort of the synthesis backend for Networks-on-Chip (NoCs), this work contributes an analysis of the performance, area and power/energy breakdown of NoC switches in 65nm technology. In particular, an architecture-level technique (control- and data-path decoupling) is deployed to derive switch implementation variants optimized for different design objectives, and is then validated against placement-aware logic synthesis. | |
Handle: | http://hdl.handle.net/11392/472268 | |
ISBN: | 978 90 382 1127 5 | |
Appare nelle tipologie: | 04.2 Contributi in atti di convegno (in Volume) |
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