The paper describes a methodological framework that aims to apply formal design and verification techniques to the domain of logic control and supervision for manufacturing systems. The methodology is based on an object-oriented approach, supported by a syntactical and semantical adaptation of the semi-formal software specification languages UML and statecharts. The modeling languages have been subsequently formalized, according to a semantics that take into account the concepts described in the IEC 61131-3 standard for industrial controllers programming, in order to prove correctness properties expressed in the temporal logic CTL. The verification process is performed by means of the model-checking tool SMV.
Design and verification of industrial logic controllers with UML and statecharts
BONFE', Marcello;
2003
Abstract
The paper describes a methodological framework that aims to apply formal design and verification techniques to the domain of logic control and supervision for manufacturing systems. The methodology is based on an object-oriented approach, supported by a syntactical and semantical adaptation of the semi-formal software specification languages UML and statecharts. The modeling languages have been subsequently formalized, according to a semantics that take into account the concepts described in the IEC 61131-3 standard for industrial controllers programming, in order to prove correctness properties expressed in the temporal logic CTL. The verification process is performed by means of the model-checking tool SMV.I documenti in SFERA sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
