In the NA62 experiment at CERN-SPS the communication between detectors and the Lowest Level (L0) trigger processor is performed via Ethernet packets, using the UDP protocol. The L0 Trigger Processor handles the signals from sub-detectors that take part to the trigger generation. In order to choose the best solution for its realization, two different approaches have been implemented. The first approach is fully based on a FPGA device while the second one joins an off-the-shelf PC to the FPGA. The performance of the two systems will be discussed and compared.

Level Zero Trigger processor for the ultra rare kaon decay experiment - NA62

Chiozzi, S.
Primo
;
GAMBERINI, Enrico
Secondo
;
Gianoli, A.;NERI, Ilaria;PETRUCCI, Ferruccio Carlo;
2016

Abstract

In the NA62 experiment at CERN-SPS the communication between detectors and the Lowest Level (L0) trigger processor is performed via Ethernet packets, using the UDP protocol. The L0 Trigger Processor handles the signals from sub-detectors that take part to the trigger generation. In order to choose the best solution for its realization, two different approaches have been implemented. The first approach is fully based on a FPGA device while the second one joins an off-the-shelf PC to the FPGA. The performance of the two systems will be discussed and compared.
Trigger concepts and systems (hardware and software), Data acquisition circuits, Trigger algorithms, Digital electronic circuits
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11392/2368782
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