The reliability and performance characterization of each non-volatile memory technology requires the thorough investigation of dedicated array test structures that mimic the real operations of a fully functional integrated product. This makes no exception also for emerging non-volatile memories like the Resistive Random Access Memory (RRAM) concept. An extensive electrical characterization activity performed on test vehicles manufactured in a CMOS backend-of-line process allowed the first glance estimation of operation modes and reliability threats typical of this technology. In this paper, it is provided a review of the most important issues like forming instabilities, optimal set/reset operation finding, and read disturb to provide a guideline either for a further technology optimization or an efficient algorithms co-design to handle these reliability/performance threats.
|Titolo:||RRAM Reliability/Performance Characterization through Array Architectures Investigations|
|Data di pubblicazione:||2015|
|Appare nelle tipologie:||04.2 Contributi in atti di convegno (in Volume)|