The paper presents test results of a front-end ASIC developed for fast timing applications with silicon pixel detectors. Implemented in a 0.13 µm CMOS process, the prototype integrates 107 read-out cells. In an area of 300 µm x 300 µm each cell incorporates a fast transimpedance amplifier with 3 ns peaking time, a Constant Fraction Discriminator (CFD) and a Time to Digital Converter (TDC). The analog front-end is optimized for signals from 1 fC to 10 fC and dissipates 1mW from a 1.2 V supply. Electrical tests of the key building blocks and system level aspects are discussed in the paper.

Experimental results from a pixel front-end for the NA62 experiment with on pixel constant fraction discriminator and 100 ps Time to Digital ConverterIEEE Nuclear Science Symposuim & Medical Imaging Conference

COTTA RAMUSINO, Angelo;CHIOZZI, Stefano;FIORINI, Massimiliano;
2010

Abstract

The paper presents test results of a front-end ASIC developed for fast timing applications with silicon pixel detectors. Implemented in a 0.13 µm CMOS process, the prototype integrates 107 read-out cells. In an area of 300 µm x 300 µm each cell incorporates a fast transimpedance amplifier with 3 ns peaking time, a Constant Fraction Discriminator (CFD) and a Time to Digital Converter (TDC). The analog front-end is optimized for signals from 1 fC to 10 fC and dissipates 1mW from a 1.2 V supply. Electrical tests of the key building blocks and system level aspects are discussed in the paper.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11392/1872116
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