We present the development of a charged particle pixel array imager operating in single hit detection mode. This challenging imaging device called GigaTracker (GTK) developed for the CERN NA62 experiment is intended to measure the position and arrival time of a pion/kaon beam with an intensity of 108*cm-2*s-1. Each particle hit is detected in position with a precision of ~100 μm and in time with a precision of 100 ps (rmsc). The readout pixel ASIC circuit in 130 nm CMOS technology comprise an array of 1800 pixels of 300 x 300 μm2. It is connected via bump bonding to an ultra fast solid state pixel sensor array matching the same pixel pattern. The performance of high rate and high timing precision together with an extreme sensitivity of the pixel channel discriminating input signals with a charge as low as 1 fC (6000 electrons) are very demanding; two imaging readout architectures are presented, one with on pixel analogue based time-to-digital-converter (TDC), the other one with digital based TDC placed at the end of each column. The design of two pixel discriminators, a constant fraction discriminator and a time-over-threshold discriminator with time walk correction technique will be discussed. The design challenges of two architectures will be also discussed. Due to the high particle intensity, a huge data flow has to be handled. Hereby only data of pixels, which actually have been hit are buffered on chip and automatically transferred off the chip. The data rate per chip is 4 Gbit/s. We present circuit design challenges and SPICE simulations of both approaches.

An ultra fast 100 ps, 100 µm 3D pixel imager

FIORINI, Massimiliano;COTTA RAMUSINO, Angelo;
2009

Abstract

We present the development of a charged particle pixel array imager operating in single hit detection mode. This challenging imaging device called GigaTracker (GTK) developed for the CERN NA62 experiment is intended to measure the position and arrival time of a pion/kaon beam with an intensity of 108*cm-2*s-1. Each particle hit is detected in position with a precision of ~100 μm and in time with a precision of 100 ps (rmsc). The readout pixel ASIC circuit in 130 nm CMOS technology comprise an array of 1800 pixels of 300 x 300 μm2. It is connected via bump bonding to an ultra fast solid state pixel sensor array matching the same pixel pattern. The performance of high rate and high timing precision together with an extreme sensitivity of the pixel channel discriminating input signals with a charge as low as 1 fC (6000 electrons) are very demanding; two imaging readout architectures are presented, one with on pixel analogue based time-to-digital-converter (TDC), the other one with digital based TDC placed at the end of each column. The design of two pixel discriminators, a constant fraction discriminator and a time-over-threshold discriminator with time walk correction technique will be discussed. The design challenges of two architectures will be also discussed. Due to the high particle intensity, a huge data flow has to be handled. Hereby only data of pixels, which actually have been hit are buffered on chip and automatically transferred off the chip. The data rate per chip is 4 Gbit/s. We present circuit design challenges and SPICE simulations of both approaches.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11392/1871940
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