The architecture and characterisation of the End Of Column demonstrator readout ASIC for the NA62 GigaTracker hybrid pixel detector is presented. This ASIC serves as a proof of principle for a pixel chip with 1800 pixels which must perform time stamping to better than 200 ps (RMS), provide 300 mm pitch position information and operate with a dead-time of 1% or less for 800MHz-1GHz beam rate. The demonstrator ASIC comprises a full test column with 45 pixels alongside other test structures. The timewalk correction mechanism employed is measurement of the time-over-threshold, coupled with an off-detector look-up table. The time to digital converter is a delay locked loop with 32 contributing delay cells fed with a 320MHz to yield a nominal bin size of 97 ps. Recently, P-in-N sensors have been bump-bonded to the ASIC and characterisation of these assemblies has begun.

Characterisation of the NA62 GigaTracker end of column readout ASIC

FIORINI, Massimiliano;
2011

Abstract

The architecture and characterisation of the End Of Column demonstrator readout ASIC for the NA62 GigaTracker hybrid pixel detector is presented. This ASIC serves as a proof of principle for a pixel chip with 1800 pixels which must perform time stamping to better than 200 ps (RMS), provide 300 mm pitch position information and operate with a dead-time of 1% or less for 800MHz-1GHz beam rate. The demonstrator ASIC comprises a full test column with 45 pixels alongside other test structures. The timewalk correction mechanism employed is measurement of the time-over-threshold, coupled with an off-detector look-up table. The time to digital converter is a delay locked loop with 32 contributing delay cells fed with a 320MHz to yield a nominal bin size of 97 ps. Recently, P-in-N sensors have been bump-bonded to the ASIC and characterisation of these assemblies has begun.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11392/1871932
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