The TDCpix ASIC is the readout chip for the Gigatracker station of the NA62 experiment. Each station of the Gigatracker needs to provide time stamping of individual particles to 200 ps-rms or better. Bump-bonded to the pixel sensor the ASIC serves an array of 40 columns x 40 pixels. The high precision time measurement of the discriminated hit signals is accomplished with a set of 40 TDCs sitting in the End-Of-Column region of the ASIC. Each TDC provides 9 channels per column. For the time-to-digital converter (TDC) a delay-locked-loop (DLL) approach is employed to achieve a constant time binning of 100ps. Simulation results show that an average rms time resolution of 33ps with a power consumption of the TDC better than 33mW per column is achieved. This contribution will present the design, simulation results and implementation challenges of the TDC.
A 9-Channel, 100 ps LSB Time-to-Digital Converter for the NA62 Gigatracker Readout ASIC (TDCpix)
FIORINI, Massimiliano
2012
Abstract
The TDCpix ASIC is the readout chip for the Gigatracker station of the NA62 experiment. Each station of the Gigatracker needs to provide time stamping of individual particles to 200 ps-rms or better. Bump-bonded to the pixel sensor the ASIC serves an array of 40 columns x 40 pixels. The high precision time measurement of the discriminated hit signals is accomplished with a set of 40 TDCs sitting in the End-Of-Column region of the ASIC. Each TDC provides 9 channels per column. For the time-to-digital converter (TDC) a delay-locked-loop (DLL) approach is employed to achieve a constant time binning of 100ps. Simulation results show that an average rms time resolution of 33ps with a power consumption of the TDC better than 33mW per column is achieved. This contribution will present the design, simulation results and implementation challenges of the TDC.I documenti in SFERA sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
