The paper describes the design of a front-end chip for hybrid pixel detectors optimized for good timing resolution (200 ps rms) and high event rate (150 kHz per pixel). Each channel consists of a fast transimpedance amplifier with 5 ns peaking time, a constant fraction discriminator (CFD), and a Time-to-Digital Converter (TDC). In order to cope with the rate requirement, a multi-event buffering scheme employing both analog and digital pipelines is implemented in each cell. This development is part of the R&D activity for the silicon tracker of the NA62 experiment at CERN. The architecture of the chip and the design of the critical building blocks are discussed in the paper.

A pixel front-end ASIC in 0.13 micron CMOS for the NA62 experiment with on pixel 100 ps Time-to-Digital Converter

COTTA RAMUSINO, Angelo;CHIOZZI, Stefano;FIORINI, Massimiliano;
2009

Abstract

The paper describes the design of a front-end chip for hybrid pixel detectors optimized for good timing resolution (200 ps rms) and high event rate (150 kHz per pixel). Each channel consists of a fast transimpedance amplifier with 5 ns peaking time, a constant fraction discriminator (CFD), and a Time-to-Digital Converter (TDC). In order to cope with the rate requirement, a multi-event buffering scheme employing both analog and digital pipelines is implemented in each cell. This development is part of the R&D activity for the silicon tracker of the NA62 experiment at CERN. The architecture of the chip and the design of the critical building blocks are discussed in the paper.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11392/1871927
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