NA62 is an experiment under development at the CERN Super Proton Synchrotron, aiming at measuring ultra rare kaon decays. The Gigatracker (GTK) detector shall combine on-beam tracking of individual particles with a time resolution of 150 ps rms. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm2 for a total rate of about 0.75 GHz. A hybrid silicon pixel detector is being developed to meet these requirements. The pixel chip for the Gigatracker (TDCpix) is under design. The TDCpix chip will feature 1800 square pixels of 300×300 μm2 arranged in a matrix of 45 rows × 40 columns. Bump-bonded to a silicon pixel sensor it shall perform time stamping of particle hits with a timing accuracy better than 200 ps rms and a detection efficiency above 99%. The chosen architecture provides full separation of the sensitive analog amplifiers of the pixel matrix from the noisy digital circuits of the TDCs and of the readout blocks. Discriminated hit signals from each pixel are transmitted to the end of column region. An array of Time to Digital Converters (TDC) is implemented at the bottom of the pixel array. The TDCs are based on time tagging the events with the fine time codes generated by Delay Locked Loops (DLL) and have a nominal time bin of ∼100 ps. Time stamps and time-over-threshold are recorded for each discriminated hit and the correction of the discriminator’s time-walk is performed off-detector. Data are continuously transmitted on four 2.4 Gb/s serial output links. A description of the on-going design of the final TDCpix is given in this paper. Design choices and some technical implementation details are presented. A prototype ASIC including the key components of this architecture has been manufactured. The achievement of specification figures such as a time resolution of the processing chain of 75 ps rms as well as charged particle time stamping with a resolution better than 200 ps rms were demonstrated experimentally. A summary of these results is also presented in this contribution. The ongoing R&D effort provided an understanding of some of the processes limiting the timing resolution that can be achieved with hybrid planar pixels. Some considerations on these aspects are discussed at last.
The TDCpix Readout ASIC: A 75 ps Resolution Timing Front-End for the Gigatrackerof theNA62 Experiment
FIORINI, Massimiliano;
2012
Abstract
NA62 is an experiment under development at the CERN Super Proton Synchrotron, aiming at measuring ultra rare kaon decays. The Gigatracker (GTK) detector shall combine on-beam tracking of individual particles with a time resolution of 150 ps rms. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm2 for a total rate of about 0.75 GHz. A hybrid silicon pixel detector is being developed to meet these requirements. The pixel chip for the Gigatracker (TDCpix) is under design. The TDCpix chip will feature 1800 square pixels of 300×300 μm2 arranged in a matrix of 45 rows × 40 columns. Bump-bonded to a silicon pixel sensor it shall perform time stamping of particle hits with a timing accuracy better than 200 ps rms and a detection efficiency above 99%. The chosen architecture provides full separation of the sensitive analog amplifiers of the pixel matrix from the noisy digital circuits of the TDCs and of the readout blocks. Discriminated hit signals from each pixel are transmitted to the end of column region. An array of Time to Digital Converters (TDC) is implemented at the bottom of the pixel array. The TDCs are based on time tagging the events with the fine time codes generated by Delay Locked Loops (DLL) and have a nominal time bin of ∼100 ps. Time stamps and time-over-threshold are recorded for each discriminated hit and the correction of the discriminator’s time-walk is performed off-detector. Data are continuously transmitted on four 2.4 Gb/s serial output links. A description of the on-going design of the final TDCpix is given in this paper. Design choices and some technical implementation details are presented. A prototype ASIC including the key components of this architecture has been manufactured. The achievement of specification figures such as a time resolution of the processing chain of 75 ps rms as well as charged particle time stamping with a resolution better than 200 ps rms were demonstrated experimentally. A summary of these results is also presented in this contribution. The ongoing R&D effort provided an understanding of some of the processes limiting the timing resolution that can be achieved with hybrid planar pixels. Some considerations on these aspects are discussed at last.I documenti in SFERA sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
