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EnglishThe authors describe a VLSI processor for pattern recognition based on content addressable memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, searching for matches on 96-bit wide patterns, in just a few 40-MHz clock cycles. We have developed this device (called the AMchip03 processor) for the silicon vertex trigger (SVT) upgrade at the Collider Detector experiment at Fermilab (CDF) using a standard-cell VLSI design methodology. This approach provides excellent pattern density; while sparing many of the complexities and risks associated to a full-custom design. The cost/performance ratio is better by well more than one order of magnitude than an FPGA-based design. This processor has a flexible and easily configurable structure that makes it suitable for applications in other experimental environments. They look forward to sharing this technology.
| Data di pubblicazione: | 2006 | |
| Titolo: | A VLSI processor for Fast Track Finding based on Content Addressable Memories | |
| Autori: | A. Annovi; A. Bardi; M. Bitossi; S. CHiozzi; C. Damiani; M. Dell' Orso; P. Giannetti; P. Giovacchini; G. Marchiori; I. Pedron; L. Sartori; F. Schifano; F. Spinella; R. Tripiccione | |
| Rivista: | IEEE TRANSACTIONS ON NUCLEAR SCIENCE | |
| Parole Chiave: | processori dedicati; VLSI | |
| Abstract: | The authors describe a VLSI processor for pattern recognition based on content addressable memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, searching for matches on 96-bit wide patterns, in just a few 40-MHz clock cycles. We have developed this device (called the AMchip03 processor) for the silicon vertex trigger (SVT) upgrade at the Collider Detector experiment at Fermilab (CDF) using a standard-cell VLSI design methodology. This approach provides excellent pattern density; while sparing many of the complexities and risks associated to a full-custom design. The cost/performance ratio is better by well more than one order of magnitude than an FPGA-based design. This processor has a flexible and easily configurable structure that makes it suitable for applications in other experimental environments. They look forward to sharing this technology. | |
| Digital Object Identifier (DOI): | 10.1109/TNS.2006.876052 | |
| Handle: | http://hdl.handle.net/11392/524718 | |
| Appare nelle tipologie: | 03.1 Articolo su rivista |
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