We describe the hardwired implementation of algorithms for Monte Carlo simulations of a large class of spin models. We have implemented these algorithms as VHDL codes and we have mapped them onto a dedicated processor based on a large FPGA device. The measured performance on one such processor is comparable to O(100) carefully programmed high-end PCs: it turns out to be even better for some selected spin models. We describe here codes that we are currently executing on the IANUS massively parallel FPGA-based system.

Simulating spin systems on IANUS, an FPGA-based computer

BELLETTI, Francesco;MANTOVANI, Filippo;SCHIFANO, Sebastiano Fabio;TRIPICCIONE, Raffaele;
2008

Abstract

We describe the hardwired implementation of algorithms for Monte Carlo simulations of a large class of spin models. We have implemented these algorithms as VHDL codes and we have mapped them onto a dedicated processor based on a large FPGA device. The measured performance on one such processor is comparable to O(100) carefully programmed high-end PCs: it turns out to be even better for some selected spin models. We describe here codes that we are currently executing on the IANUS massively parallel FPGA-based system.
2008
Belletti, Francesco; M., Cotallo; A., Cruz; L. A., Fernandez; A., Gordillo; A., Maiorano; Mantovani, Filippo; E., Marinari; V., Martin Mayor; A., Muno...espandi
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11392/521400
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