Flash memories are normally erased by means of high-field electron tunnelling from the floating gate into the source. As a consequence the time needed is generally two orders of magnitude larger (≈ 1 ms vs. ≈ 10 μs) than that used for writing, and is obtained by means of much higher currents due to channel hot electrons. It is important therefore to determine whether it is possible to reduce the erase time, in order to make it comparable with that used for writing. With regard to such a problem, this work describes the results of a comprehensive and detailed characterization of flash structures aimed at evaluating how ultra-short, high voltage erasing pulses affect the reliability of the device. © 1994.
Characterization of flash structures erased with ultra-short pulses
OLIVO, Piero
1994
Abstract
Flash memories are normally erased by means of high-field electron tunnelling from the floating gate into the source. As a consequence the time needed is generally two orders of magnitude larger (≈ 1 ms vs. ≈ 10 μs) than that used for writing, and is obtained by means of much higher currents due to channel hot electrons. It is important therefore to determine whether it is possible to reduce the erase time, in order to make it comparable with that used for writing. With regard to such a problem, this work describes the results of a comprehensive and detailed characterization of flash structures aimed at evaluating how ultra-short, high voltage erasing pulses affect the reliability of the device. © 1994.I documenti in SFERA sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
