Special session on overcoming reliability and energy-efficiency challenges with silicon photonics for future manycore computing

Silicon photonics has emerged in recent years as one of the most promising solutions to overcome the challenge of worsening chip-scale communication performance with technology scaling. Recent breakthroughs in silicon photonic device fabrication and CMOS integration have presented computer designers with an opportunity to devise on-chip optical networks that have significant advantages in bandwidth density, energy-efficiency, and propagation delay over traditional electrical solutions. Not surprisingly, the challenge of designing chip-scale silicon photonic communication fabrics is today actively being pursued by a number of researchers worldwide. Many semiconductor companies (e.g., Intel, IBM) have begun investing heavily into silicon photonics and are releasing functional prototypes. However, silicon photonic interconnects have high susceptibility to faults due to several factors such as homodyne and heterodyne crosstalk, process variations, and thermal fluctuations. Moreover, photonic devices can have a significant power dissipation footprint, which can increase further when compensating for potential faults. New network-centric circuits, architectures, tools, and protocols are required to overcome these challenges. This special session focuses on the overarching goals of enabling high fault resilience and energy-efficiency in emerging silicon photonic on-chip networks.