Energy-Efficiency Evaluation of Intel KNL for HPC Workloads

In this work we focus on energy performance of the Knights Landing Xeon Phi, the latest many-core architecture processor introduced by Intel for the HPC market. We take into account the 64-core Xeon Phi 7230, and analyze the computing and energy efficiency using both the on-chip MCDRAM and the off-chip DDR4 memory as main storage for the application data domain. As a benchmark application we use a Lattice Boltzmann code heavily optimized for this architecture, and implemented using different memory data layouts to store the data-domain. We then assess the energy consumption using different data-layouts, memory configurations (DDR4 or MCDRAM), and number of threads per core.