Cost-effective and flexible asynchronous interconnect technology for GALS networks-on-chip

Fine-grained power management of largely-integrated manycore systems is becoming mainstream in order to deal with tight power budgets. As a result, some level of asynchrony is becoming inevitable for efficient system-level operation. Asynchronous interconnection networks naturally provide such asynchrony, however their wide industrial uptake depends on the capability to overcome two fundamental barriers: their area and dynamic power overhead as well as the limited computer-aided design (CAD) tool support for their automated design. This paper presents a novel design point (i.e., a switch architecture and a hierarchical synthesis toolflow for network assembly) for on-chip asynchronous communication, combining design flexibility with small footprint and cost effectiveness.