Fine-grained power management of largely-integrated manycore systems is becoming mainstream in order to deal with tight power budgets. As a result, some level of asynchrony is becoming inevitable for efficient system-level operation. Asynchronous interconnection networks naturally provide such asynchrony, however their wide industrial uptake depends on the capability to overcome two fundamental barriers: their area and dynamic power overhead as well as the limited computer-aided design (CAD) tool support for their automated design. This paper presents a novel design point (i.e., a switch architecture and a hierarchical synthesis toolflow for network assembly) for on-chip asynchronous communication, combining design flexibility with small footprint and cost effectiveness.

Cost-effective and flexible asynchronous interconnect technology for GALS networks-on-chip

Bertozzi, Davide;Miorandi, Gabriele;Tala, Mahdi;
2017

Abstract

Fine-grained power management of largely-integrated manycore systems is becoming mainstream in order to deal with tight power budgets. As a result, some level of asynchrony is becoming inevitable for efficient system-level operation. Asynchronous interconnection networks naturally provide such asynchrony, however their wide industrial uptake depends on the capability to overcome two fundamental barriers: their area and dynamic power overhead as well as the limited computer-aided design (CAD) tool support for their automated design. This paper presents a novel design point (i.e., a switch architecture and a hierarchical synthesis toolflow for network assembly) for on-chip asynchronous communication, combining design flexibility with small footprint and cost effectiveness.
9781509064472
Asynchronous; Bundled-data; GALS; Network-On-chip; Transition signalling; Computer Networks and Communications; Hardware and Architecture; Instrumentation; Electrical and Electronic Engineering
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11392/2383383
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