Simulations of the software-defined flash

In the last 30 years all software applications and Operating Systems (OSes) which make use of persistent storage architectures have been designed to work with HDDs. However, SSDs are physically and architecturally different from HDDs; in particular, SSDs need to execute a specific algorithm for translating host commands: the Flash Translation Layer (FTL). Basically, the main role of FTL it to mimic the behavior of a traditional HDD and to enable the usage of SSDs in any electronic systems without acting on the software stack. The main drawback of FTL is the Write Amplification Factor (WAF) which reduces both drive bandwidth and NAND flash reliability. Especially in the enterprise market and hyperscale data centers, performance and reliability losses induced by WAF are not tolerable. To deal with the above mentioned challenges, in the past few years software developers of hyperscale data centers have shown a growing interest for Software-Defined Flash (SDF), which leverages a new SSD design approach called Host-based FTL (HB-FTL). Thanks to SDF and HB-FTL it is possible to establish a native communication between the host system and the SSD. Basically, NAND flash memories can be directly addressed by the host without any further translation or manipulation layer. As a result, the write amplification phenomenon is removed and both performance and reliability are improved. However, according to the Open-Channel specifications, to enable the use of HB-FTL in SDF, the design of the SSD controller has to be slightly modified and its internal architecture has to be exposed to the host system. In this regard, the Open-Power initiative helps to provide a clear path to the HBFTL execution, whereas the Open-Channel approach tries to define a standard for future SSD controllers, custom designed for SDF. This chapter describes a simulation model that can be used to simulate SDF architectures exploiting the Open-Channel standard proposed by the Open-Power initiative.