Resistive RAM (RRAM) technology gathered a significant interest in the last decade for system-on-chip applications in silicon-based CMOS technologies like microcontrollers for wireless sensor nodes in the Internet of Things environment, and automotive electronics. Enterprise storage platforms like high performance Solid State Drives (SSD) are considering to adopt this technology as a possible storage medium due to its forecasted high reliability, fast access time, and a number of benefits like the native multi-level capability and bit-alterability. In this chapter, we address the basic principles of the RRAM technology starting from the typical cell structure and the physical mechanisms involved in the storage of the information. Thorough analyses of the operations, as well as of the yield and reliability are presented. Then, a review of the most common integration concepts from the 1T-1R to the forecasted 3D cross-point arrays are presented. A brief investigation of the RRAM architectures will help the reader in understanding the density limitations of this technology compared to decananometer scale multi-bit per cell planar and 3D NAND Flash architectures.

Resistive RAM technology for SSDs

ZAMBELLI, Cristian;OLIVO, Piero
2017

Abstract

Resistive RAM (RRAM) technology gathered a significant interest in the last decade for system-on-chip applications in silicon-based CMOS technologies like microcontrollers for wireless sensor nodes in the Internet of Things environment, and automotive electronics. Enterprise storage platforms like high performance Solid State Drives (SSD) are considering to adopt this technology as a possible storage medium due to its forecasted high reliability, fast access time, and a number of benefits like the native multi-level capability and bit-alterability. In this chapter, we address the basic principles of the RRAM technology starting from the typical cell structure and the physical mechanisms involved in the storage of the information. Thorough analyses of the operations, as well as of the yield and reliability are presented. Then, a review of the most common integration concepts from the 1T-1R to the forecasted 3D cross-point arrays are presented. A brief investigation of the RRAM architectures will help the reader in understanding the density limitations of this technology compared to decananometer scale multi-bit per cell planar and 3D NAND Flash architectures.
978-3-319-51734-6
978-3-319-51735-3
Electrical and Electronic Engineering
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11392/2373878
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