Compressed Sensing (CS) can be introduced in the processing chain of a sensor node as a mean to globally reduce its operating cost, while maximizing the quality of the acquired signal. We exploit CS as a simple early-digital compression stage that performs a multiplication of the signal by a matrix. The operating costs (e.g., the consumed power) of such an encoding stage depend on the number of rows of the matrix, but also on the value and position of the rows' coefficients. Our novel design flow yields optimized sparse matrices with very few rows. It is a non-trivial extension of the rakeness-based approach to CS and yields an extremely lightweight stage implemented by a very small number of possibly signed sums with an excellent compression performance. By means of a general signal model we explore different corners of the design space and show that, for example, our method is capable of compressing the signal by a factor larger than 2.5 while not considering 30% of the original samples (so that they may not be acquired at all, leaving the analog front-end and ADC stages inactive) and by processing each of the considered samples with not more than three signed sums.

Rakeness-Based Design of Low-Complexity Compressed Sensing

PARESCHI, Fabio;SETTI, Gianluca
2017

Abstract

Compressed Sensing (CS) can be introduced in the processing chain of a sensor node as a mean to globally reduce its operating cost, while maximizing the quality of the acquired signal. We exploit CS as a simple early-digital compression stage that performs a multiplication of the signal by a matrix. The operating costs (e.g., the consumed power) of such an encoding stage depend on the number of rows of the matrix, but also on the value and position of the rows' coefficients. Our novel design flow yields optimized sparse matrices with very few rows. It is a non-trivial extension of the rakeness-based approach to CS and yields an extremely lightweight stage implemented by a very small number of possibly signed sums with an excellent compression performance. By means of a general signal model we explore different corners of the design space and show that, for example, our method is capable of compressing the signal by a factor larger than 2.5 while not considering 30% of the original samples (so that they may not be acquired at all, leaving the analog front-end and ADC stages inactive) and by processing each of the considered samples with not more than three signed sums.
Mangia, Mauro; Pareschi, Fabio; Cambareri, Valerio; Rovatti, Riccardo; Setti, Gianluca
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11392/2365111
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