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EnglishRadio communication is among the most energy consuming tasks in wireless sensor nodes. Reducing the amount of data to be transmitted holds a large power saving potential. The combination of compressed sensing (CS) and local signal parameter estimation can achieve a massive data rate reduction in applications where the primary interest is in the acquisition of a scalar feature of the signal rather than the reconstruction of the entire waveform. In this paper, We propose a compressed estimator, building upon an enhancement of the typical CS signal-modulation scheme via punctured sampling. Specifically, a subset of signal samples and associated weighting coefficients are chosen so as to minimize node power consumption while achieving a given estimation performance. We detail a corresponding puncturing algorithm and present the design of an integrated digital compressed estimation unit in 28nm FDSOI CMOS. In a concrete case study, local estimation combined with subsampling is shown to result in a power reduction of up to an order of magnitude with respect to the standard solution of sampling and transmitting samples for off-board processing.
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| Titolo: | An architecture for low-power compressed sensing and estimation in wireless sensor nodes |
| Autori: | |
| Data di pubblicazione: | 2014 |
| Abstract: | Radio communication is among the most energy consuming tasks in wireless sensor nodes. Reducing the amount of data to be transmitted holds a large power saving potential. The combination of compressed sensing (CS) and local signal parameter estimation can achieve a massive data rate reduction in applications where the primary interest is in the acquisition of a scalar feature of the signal rather than the reconstruction of the entire waveform. In this paper, We propose a compressed estimator, building upon an enhancement of the typical CS signal-modulation scheme via punctured sampling. Specifically, a subset of signal samples and associated weighting coefficients are chosen so as to minimize node power consumption while achieving a given estimation performance. We detail a corresponding puncturing algorithm and present the design of an integrated digital compressed estimation unit in 28nm FDSOI CMOS. In a concrete case study, local estimation combined with subsampling is shown to result in a power reduction of up to an order of magnitude with respect to the standard solution of sampling and transmitting samples for off-board processing. |
| Handle: | http://hdl.handle.net/11392/2338439 |
| ISBN: | 9781479934324 9781479934324 |
| Appare nelle tipologie: | 04.2 Contributi in atti di convegno (in Volume) |
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http://hdl.handle.net/11392/2338439
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