The current trend to migrate wireless applications to higher frequencies to obtain broader bandwidths and therefore higher transmission throughput has driven semiconductor companies to develop faster devices with high integration. This has come along with some complications in device characterization and modeling. Semiconductor layout dimensions are close to thewavelength of the electromagnetic (EM) wave propagating through it, and therefore the classical equivalent circuit approaches for the description of device parasitics are not representative of what is actually happening at the device and circuit level. In this sense, a relatively new way to analyze the parasitics has evolved, which is based on EM characterization of the parasitic network. This chapter aims to describe methodologies and techniques for de-embedding device measurements from extrinsic measurements by characterizing the parasitic network surrounding the intrinsic device, through the use of a three-dimensional (3D) physical model of the network and its electromagnetic analysis. The electromagnetic assessment is carried out employing 3D EM solvers and internal ports. In the first part, four different de-embedding procedures applied to field-effect transistors (FETs) for monolithic microwave integrated circuit (MMIC) design are presented. In the second part, the de-embedding of FET devices for hybrid circuit design purposes is described.
Electromagnetic-Analysis-Based Transistor De-embedding and Related Radio-Frequency Amplifier Design
VANNINI, Giorgio
2014
Abstract
The current trend to migrate wireless applications to higher frequencies to obtain broader bandwidths and therefore higher transmission throughput has driven semiconductor companies to develop faster devices with high integration. This has come along with some complications in device characterization and modeling. Semiconductor layout dimensions are close to thewavelength of the electromagnetic (EM) wave propagating through it, and therefore the classical equivalent circuit approaches for the description of device parasitics are not representative of what is actually happening at the device and circuit level. In this sense, a relatively new way to analyze the parasitics has evolved, which is based on EM characterization of the parasitic network. This chapter aims to describe methodologies and techniques for de-embedding device measurements from extrinsic measurements by characterizing the parasitic network surrounding the intrinsic device, through the use of a three-dimensional (3D) physical model of the network and its electromagnetic analysis. The electromagnetic assessment is carried out employing 3D EM solvers and internal ports. In the first part, four different de-embedding procedures applied to field-effect transistors (FETs) for monolithic microwave integrated circuit (MMIC) design are presented. In the second part, the de-embedding of FET devices for hybrid circuit design purposes is described.I documenti in SFERA sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
