Exposing Reliability/Performance Trade-Off in Non-Volatile Memories through Erratic Bits Signature Classification

The erratic bits phenomenon in non-volatile memories (NVM) has been evidenced in several technologies as a main reliability detractor. Usually this issue is handled by repair strategies which spans from static redundancy to dynamic correction codes. This evidences a trade-off in reliability/performance domain that is due to the limitation in the repair resources amount and correction strength. In this work we expose this trade-off in different NVM technologies such as embedded NOR Flash and Phase Change Memories through an accurate EB testing, signature classification procedure, and Chip Failure Rate estimation.