The current high levels of on-chip integration allow for the implementation of increasingly complex systems-on-chip (SoCs), consisting of heterogeneous components such as general-purpose processors, DSPs, coprocessors, memories, I/O units, and dedicated hardware accelerators. In this context, multiprocessor systems-on-chip (MPSoCs) have emerged as an effective solution to meet the demand for computational power posed by application domains such as network processors and and parallel media processors. MPSoCs combine the advantages of parallel processing with the high integration levels of SoCs. It is expected that future MPSoCs will integrate hundreds of processing units (PUs) and storage elements, and their performance will be increasingly interconnect-dominated [40]. Interconnect technology and architecture will become the limiting factor for achieving operational goals, and the efficient design of low-power, high-performance on-chip communication architectures will pose novel challen...

SoC Communication Architectures: from Interconnection Buses to Packet-Switched NoCs

BERTOZZI, Davide;
2009

Abstract

The current high levels of on-chip integration allow for the implementation of increasingly complex systems-on-chip (SoCs), consisting of heterogeneous components such as general-purpose processors, DSPs, coprocessors, memories, I/O units, and dedicated hardware accelerators. In this context, multiprocessor systems-on-chip (MPSoCs) have emerged as an effective solution to meet the demand for computational power posed by application domains such as network processors and and parallel media processors. MPSoCs combine the advantages of parallel processing with the high integration levels of SoCs. It is expected that future MPSoCs will integrate hundreds of processing units (PUs) and storage elements, and their performance will be increasingly interconnect-dominated [40]. Interconnect technology and architecture will become the limiting factor for achieving operational goals, and the efficient design of low-power, high-performance on-chip communication architectures will pose novel challen...
2009
9781439807552
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11392/1735148
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