In this paper we propose a prototype of a Spread Spectrum Clock Generator which is the first known specifically meant for 3 GHz Serial ATA-II (SATA-II) applications. A further innovative aspect of our prototype is that it takes advantage of a chaotic PAM as driving signal, instead of a triangular signal as in all spread spectrum generators proposed so far in the literature for SATA-II. In this way, we are able to obtain the optimal theoretical EMI reduction by avoiding the periodicity of the modulated clock and completely flattening the peaks in the power spectral density. We also show that, despite the fact that such an unconventional, a-periodic modulating signal is used, the clock can be recovered exploiting a standard CDR circuit at the receiver side of the SATA-II bus. The circuit prototype has been implemented in 0.13 um CMOS technology and achieves a peak reduction greater than 14 dB measured at RBW = 100 kHz, which is better than any other prototypes presented in the literature. The estimated random jitter is 5.4 ps rms, while the chip active area is 0.27 x 0.78 mm^2 and the power consumption is as low as 14.7 mW.
A 3-GHz serial ATA spread-spectrum clock generator employing a chaotic PAM modulation
PARESCHI, Fabio;SETTI, Gianluca;
2010
Abstract
In this paper we propose a prototype of a Spread Spectrum Clock Generator which is the first known specifically meant for 3 GHz Serial ATA-II (SATA-II) applications. A further innovative aspect of our prototype is that it takes advantage of a chaotic PAM as driving signal, instead of a triangular signal as in all spread spectrum generators proposed so far in the literature for SATA-II. In this way, we are able to obtain the optimal theoretical EMI reduction by avoiding the periodicity of the modulated clock and completely flattening the peaks in the power spectral density. We also show that, despite the fact that such an unconventional, a-periodic modulating signal is used, the clock can be recovered exploiting a standard CDR circuit at the receiver side of the SATA-II bus. The circuit prototype has been implemented in 0.13 um CMOS technology and achieves a peak reduction greater than 14 dB measured at RBW = 100 kHz, which is better than any other prototypes presented in the literature. The estimated random jitter is 5.4 ps rms, while the chip active area is 0.27 x 0.78 mm^2 and the power consumption is as low as 14.7 mW.I documenti in SFERA sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
