The continuous demand for NAND flash memories with higher performance and storage capabilities pushes the manufactures towards the limits of present technologies and to explore new solutions, both from the physical and the architectural point of view. The memory reliability represents one of the major antagonist towards this un-stoppable technological evolution, since the correct operations must be assured not only when a new product is presented, but they must be demonstrated for the entire life cycle. In particular, the minimum number of write operations and the ability of keeping unaltered the stored information for years and years must be guaranteed. In this chapter the principal reliability mechanisms affecting the traditional floating-gate NAND flash memories will be addressed: the physical aspects caused by charge transport and trapping in thin insulator layers as well as the in-correct behaviors related to the array architecture. It will also shown as these ef-fects increase dramatically their impact when Multi Level Cells (MLC) are con-sidered. New emerging mechanisms, such as Gate-Induce Drain Leakage (GIDL), Random Telegraph Noise (RTN) and temperature instabilities will also be ad-dressed.
Reliability of NAND Flash Memories
ZAMBELLI, Cristian;CHIMENTON, Andrea;OLIVO, Piero
2010
Abstract
The continuous demand for NAND flash memories with higher performance and storage capabilities pushes the manufactures towards the limits of present technologies and to explore new solutions, both from the physical and the architectural point of view. The memory reliability represents one of the major antagonist towards this un-stoppable technological evolution, since the correct operations must be assured not only when a new product is presented, but they must be demonstrated for the entire life cycle. In particular, the minimum number of write operations and the ability of keeping unaltered the stored information for years and years must be guaranteed. In this chapter the principal reliability mechanisms affecting the traditional floating-gate NAND flash memories will be addressed: the physical aspects caused by charge transport and trapping in thin insulator layers as well as the in-correct behaviors related to the array architecture. It will also shown as these ef-fects increase dramatically their impact when Multi Level Cells (MLC) are con-sidered. New emerging mechanisms, such as Gate-Induce Drain Leakage (GIDL), Random Telegraph Noise (RTN) and temperature instabilities will also be ad-dressed.I documenti in SFERA sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
