Scalable nonlinear FET model based on a distributed parasitic network description

Electron device modeling requires accurate descriptions of parasitic passive structures connecting the intrinsic electron device to the external world. In conventional approaches, the parasitic phenomena are described by a network of lumped elements. As an alternative, a distributed description can be conveniently adopted. This choice has been proved very appropriate when dealing with device scaling and very high operating frequencies. In this paper, a distributed parasitic network is adopted for the very first time in association with a nonlinear electron device model. In particular, it is shown how an equivalent intrinsic device and a suitably-defined distributed parasitic network can be accurately defined and modeled on the basis of standard measurements and easy electromagnetic simulations. Wide experimental validation based on GaAs PHEMTs is provided, showing accurate prediction capabilities both under small- and large-signal conditions. The proposed model is shown to perform optimally even after periphery scaling.