This paper presents a study of the effects on the elec. trical behavior of BiCMOS digital circuits induced by bridging faults, whose resistance value is shown to have a strong impact on the static and dynamic behavior of faulty gates and of their fanout gates. The problem of fault detection is addressed considering different testing techniques (current monitoring, functional, and delay testing). Electrical simulation has been used to investigate the main differences between BiCMOS and CMOS circuits. It is shown that, because of the large driving capability of BJT's the detection of bridging faults in BiCMOS circuits is more difficult than in the CMOS case when functional or delay testing is used whereas it becomes more effective when adopting current monitoring. © 1993 IEEE
Analysis of Resistive Bridging Fault Detection in BiCMOS Digital ICs
OLIVO, Piero;
1993
Abstract
This paper presents a study of the effects on the elec. trical behavior of BiCMOS digital circuits induced by bridging faults, whose resistance value is shown to have a strong impact on the static and dynamic behavior of faulty gates and of their fanout gates. The problem of fault detection is addressed considering different testing techniques (current monitoring, functional, and delay testing). Electrical simulation has been used to investigate the main differences between BiCMOS and CMOS circuits. It is shown that, because of the large driving capability of BJT's the detection of bridging faults in BiCMOS circuits is more difficult than in the CMOS case when functional or delay testing is used whereas it becomes more effective when adopting current monitoring. © 1993 IEEEI documenti in SFERA sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
