This work presents novel ideas to improve design for testability (DFT) of CMOS digital IC’s. In particular, two new techniques are suggested for non-stuck-at faults that avoid the drawbacks of previous solutions. Furthermore, an original method is proposed for on-line detection of delay faults, so far not yet considered in the context of DFT. All suggested schemes require limited extra hardware and minimal degradation of circuit performance. © 1990 IEEE

Novel Design for Testability Schemes for CMOS ICs

OLIVO, Piero;
1990

Abstract

This work presents novel ideas to improve design for testability (DFT) of CMOS digital IC’s. In particular, two new techniques are suggested for non-stuck-at faults that avoid the drawbacks of previous solutions. Furthermore, an original method is proposed for on-line detection of delay faults, so far not yet considered in the context of DFT. All suggested schemes require limited extra hardware and minimal degradation of circuit performance. © 1990 IEEE
1990
M., Favalli; Olivo, Piero; M., Damiani; B., Ricco'
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11392/462044
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