The fault simulation of resistive bridging faults inside complex CMOS macro-gates requires proper evaluation of resistances, in order to correctly determine realistic fault coverages. To this purpose, the present work illustrates a novel approach applicable to a large category of faults (bridgings, transistor stuck-ons and node stuck-ats) giving rise to resistive paths between power supply and ground, hence being all indicated by the general term of “bridging faults.” Such a method, avoiding single-fault injection procedure, consists of a fault analysis performed inside macro-gates aimed at determining the threshold resistance discriminating whether or not a given fault is detectable as a logic error; this analysis is performed inside CMOS macro-gates whose output is observable, as determined by means of any method and/or simulator. Finally, to fully characterize the quality of a test sequence with regard to resistive bridging faults, a new definition of fault coverage is presented, because the common concept of fault detection is not applicable to parametric faults. © 1993 IEEE
Fault Simulation of Parametric Bridging Faults in CMOS ICs
OLIVO, Piero;
1993
Abstract
The fault simulation of resistive bridging faults inside complex CMOS macro-gates requires proper evaluation of resistances, in order to correctly determine realistic fault coverages. To this purpose, the present work illustrates a novel approach applicable to a large category of faults (bridgings, transistor stuck-ons and node stuck-ats) giving rise to resistive paths between power supply and ground, hence being all indicated by the general term of “bridging faults.” Such a method, avoiding single-fault injection procedure, consists of a fault analysis performed inside macro-gates aimed at determining the threshold resistance discriminating whether or not a given fault is detectable as a logic error; this analysis is performed inside CMOS macro-gates whose output is observable, as determined by means of any method and/or simulator. Finally, to fully characterize the quality of a test sequence with regard to resistive bridging faults, a new definition of fault coverage is presented, because the common concept of fault detection is not applicable to parametric faults. © 1993 IEEEI documenti in SFERA sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
