The NA62 experiment aims to measure the ultra-rare decay of a kaon into a pion and neutrinoantineutrino pair at the Super-Proton-Synchrotron (SPS) accelerator at CERN. This measurement could provide a decisive test of the Standard Model. The upstream detector, namely the Giga-tracker (GTK), will perform the momentum and angular measurements of the incoming beam with sub-ns time resolution in order to provide a tight time coincidence between the kaon and the pion tracks [1, 2]. In order to achieve the required time resolution of 100 ps (rms) it is necessary to compensate for the discriminator time-walk [3]. For this purpose two complementary architectures have been explored. The first one is based on a simple pixel cell, featuring a front-end amplifier followed by a leading-edge discriminator and a transmission line driver and by high precision Time-to-Digital-Converters (TDC) in the end of column shared by a group of pixels [4, 5]. The second option aims to maximize the on-pixel signal processing using a Constant-Fraction-Discriminator (CFD) followed by a TDC on each cell [6, 7, 8]. The two architectures have been designed and produced as small-size prototypes in 130 nm CMOS technology and the ASICs were bump-bonded to 200 μm thick silicon sensors. The recent experimental results obtained from the prototype assemblies during laboratory and beam tests are described in this paper.
Results from the gigatracker prototypes: Two pixel front-end ASICs with sub-ns time resolution for the NA62 experiment
CARASSITI, Vittore;FIORINI, Massimiliano;PETRUCCI, Ferruccio Carlo;COTTA RAMUSINO, Angelo;
2011
Abstract
The NA62 experiment aims to measure the ultra-rare decay of a kaon into a pion and neutrinoantineutrino pair at the Super-Proton-Synchrotron (SPS) accelerator at CERN. This measurement could provide a decisive test of the Standard Model. The upstream detector, namely the Giga-tracker (GTK), will perform the momentum and angular measurements of the incoming beam with sub-ns time resolution in order to provide a tight time coincidence between the kaon and the pion tracks [1, 2]. In order to achieve the required time resolution of 100 ps (rms) it is necessary to compensate for the discriminator time-walk [3]. For this purpose two complementary architectures have been explored. The first one is based on a simple pixel cell, featuring a front-end amplifier followed by a leading-edge discriminator and a transmission line driver and by high precision Time-to-Digital-Converters (TDC) in the end of column shared by a group of pixels [4, 5]. The second option aims to maximize the on-pixel signal processing using a Constant-Fraction-Discriminator (CFD) followed by a TDC on each cell [6, 7, 8]. The two architectures have been designed and produced as small-size prototypes in 130 nm CMOS technology and the ASICs were bump-bonded to 200 μm thick silicon sensors. The recent experimental results obtained from the prototype assemblies during laboratory and beam tests are described in this paper.I documenti in SFERA sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
