Non Volatile Memory Partitioning Scheme for Technology-based Performance-Reliability Trade-off

The need to improve nonvolatile memories reliability in embedded systems is a key design concern. We here propose a methodology, managed by the memory controller, that optimizes the data reliability at the physical level for critical data whereas exploiting the transaction performances for non-critical data. The reliability-performance trade-off is obtained by partitioning the memory addressable space in different functional blocks, each on written by means of a specific optimized writing algorithm. The method feasibility is demonstrated by a case study exploiting Phase Change Memories (PCM) features.